The present invention relates to the field of testing semiconductor devices and integrated circuits for defects, and more particularly relates to testing using a multi-parameter threshold.
In the manufacture of semiconductor devices, methods are performed for testing a device and determining if it is an acceptable device or if it contains defects before selling such a product to a customer. If the results of the test are within a manufacturer""s tolerance levels then the device is presumably a non-defective device and may be sold to a customer. If the results of the test are not within the manufacturer""s tolerance levels then the device is a defective device and cannot be sold to a customer.
One method for testing a device for defects is IDDQ testing. IDDQ derives from quiescent IDD which is the current drawn by a VDD power supply. The VDD power supply is typically held at a voltage above ground and fixed within narrow bounds. The other power supply is typically called Vss and is taken to ground. In IDDQ testing, an electronic device may be tested by measuring the current while the device is in the quiescent state. Since defects often result in significant leakage currents, measuring the quiescent current allows defects such as gate oxide shorts, bridge detects, etc. to be detected. If the IDDQ current is above a preset threshold, then the device may be classified as defective and not sold to the customer.
However, technology scaling challenges the effectiveness of current-based techniques such as IDDQ testing. Elevated leakage current in scaled technologies increases the intrinsic leakage current of integrated circuits. This diminishes the sensitivity and degrades the required signal to noise ratio for IDDQ testing. One way to deal with this problem is to lower the intrinsic leakage current prior to performing IDDQ testing. However, leakage reduction techniques are not as favorable in aggressively scaled technologies. It is therefore desirable to find a testing solution for very fast and high performance integrated circuits that are susceptible to elevated background leakage current.